FIG. 1 illustrates, and indicates as a whole by the reference number 1, a known step-down DC-DC converter usable as a voltage regulator. In particular, to provide an example, in FIG. 1 a DC-DC converter is illustrated having a Buck circuit configuration; however, this should not be deemed limiting, in that considerations altogether similar to the ones that are made in what follows for this type of circuit configuration also apply to DC-DC converters having Boost and Flyback circuit configurations.
According to what is illustrated in FIG. 1, the DC-DC converter comprises an input terminal 2, set, when in use, at an input voltage VIN, and an output terminal 4 supplying an output voltage VOUT lower than the input voltage VIN.
The DC-DC converter 1 comprises a first and a second switch 6, 8, typically formed of bipolar transistors or p-channel or n-channel MOSFET transistors, the opening and closing whereof are controlled in phase by a driving stage 10. In particular, the first switch 6 presents a first terminal connected to the input terminal 2 of the DC-DC converter 1, and a second terminal connected, via a diode 12, to ground, whilst the second switch 8 presents a first terminal also connected to the input terminal 2 of the DC-DC converter 1 via a sense resistor 14, and a second terminal connected, via the diode 12, to ground.
The DC-DC converter 1 further comprises an inductor 16 connected between the second terminals of the switches 6 and 8 and the output terminal 4; a capacitor 18 connected between the output terminal 4 and ground; and a voltage divider 20 formed of two resistors 22, 24 connected between the output terminal 4 and ground and presenting an intermediate node 26 on which a division voltage VFB is present, which is proportional, through the division ratio, to the output voltage VOUT supplied by the DC-DC converter 1.
The DC-DC converter 1 moreover comprises a differential voltage error amplifier (VEA) 28 presenting an inverting terminal connected to the intermediate node 26 of the voltage divider 20 and receiving from the latter the division voltage VFB, a non-inverting terminal receiving a reference voltage VREF, and an output terminal supplying an intermediate voltage VM and connected to a non-inverting terminal of a differential comparator 30, known as PWM (Pulse Width Modulator) comparator, and hereinafter indicated by this name, which in turn presents an inverting terminal connected to the output terminal of an oscillator 32 supplying a comparison voltage VC presenting a sawtooth waveform and having a preset frequency upon which the switching frequency of the DC-DC converter 1 depends, and an output terminal connected to the input of the driving stage 10 of the switches 6 and 8.
In particular, the PWM comparator 30 basically acts as a pulse width modulator and supplies at an output a voltage having a square waveform, the duty cycle whereof is a function of the voltage supplied by the voltage error amplifier 28, and the frequency whereof depends upon the frequency of the comparison voltage VC supplied by the oscillator 32.
Finally, the DC-DC converter 1 comprises a fixed threshold current limiting stage having the purpose of protecting the DC-DC converter 1 against current overloads and basically consisting of a differential comparator 34, hereinafter indicated as CURL comparator, presenting an inverting terminal and a non-inverting terminal connected across the sense resistor 14 and an output terminal issuing a limiting signal VL supplied to the driving stage 10; in particular, the CURL comparator 34 carries out the comparison between the voltage present across the sense resistor 14 and a preset reference voltage programmed inside it: if the voltage present across the sense resistor 14 is less than or equal to the reference voltage programmed inside it, then the limiting signal VL switches to a low logic level indicative of the absence of overloads, and the driving stage 10 continues to operate in a normal way, controlling opening and closing of the switches 6 and 8 at a nominal switching frequency correlated to the frequency of the comparison voltage VC supplied by the oscillator 32, whereas if the voltage present across the sense resistor 14 is greater than the reference voltage programmed inside it, then the limiting signal VL switches to a high logic level indicative of the presence of overloads, and, in response to the switching of the limiting signal VL from the low logic level to the high logic level, the driving stage 10 controls opening of the switches 6 and 8, so as to interrupt the current supplied to the DC-DC converter 1.
The opening of the switch 8 causes the voltage across the sense resistor 14 to become zero, and thus causes the limiting signal VL generated by the CURL comparator 34 to switch again to the low logic level, and consequently the driving stage 10 to return to conditions of normal operating.
As a result, as long as the overload persists, the limiting signal VL supplied by the CURL comparator 34 continues to switch between the high and low logic levels, thus generating a pulse train which, when supplied to the driving stage 10, causes switching of the operation of the DC-DC converter 1 between a normal operation, in which opening and closing of the switches 6 and 8 is controlled at a preset frequency correlated to that of the sawtooth voltage supplied by the PWM comparator 30, and an current limitation operation, in which opening of the switches 6 and 8 is controlled in order to interrupt the current supplied to the DC-DC converter 1.
The operation of the DC-DC converter 1 is in itself known and will here be referred to solely as regards the aspects necessary for understanding the problems lying at the basis of the present invention. In particular, the DC-DC converter 1 presents a single operating mode in which the voltage error amplifier 28 carries out regulation of the output voltage VOUT so that this remains constant as the current required by the load connected to the output terminal of the DC-DC converter 1 varies.
In FIG. 2 there is illustrated and indicated by 40 a known step-down DC-DC converter usable as a battery charger, in which identical parts or parts equivalent to the ones of the DC-DC converter 1 are designated with the same reference numbers.
In particular, the DC-DC converter 40 differs from the DC-DC converter 1 by further comprising a sense resistor 42 connected in series to the inductor 16 and interposed between the inductor 16 and the output terminal 4 of the DC-DC converter 40; a filtering stage 44, made typically using an operational amplifier and presenting a first input terminal and a second input terminal connected across the sense resistor 42, and an output terminal supplying a voltage equal to the filtered voltage VFR present across the sense resistor 42; and a differential current error amplifier (CEA) 46 presenting an inverting terminal connected to the output terminal of the filtering stage 44, a non-inverting terminal receiving a reference voltage VR, and an output terminal connected to the inverting terminal of the PWM comparator 30 through a decoupling diode 48, which presents the anode terminal connected to the inverting terminal of the PWM comparator 30 and the cathode terminal connected to the output terminal of the current error amplifier 46.
In particular, the reference voltage VR is generated by causing a constant current, supplied by a current generator 52 connected in series to a resistor 50, to flow in the resistor 50 itself; the reference voltage thus obtained is then taken across the resistor 50.
The operation of the DC-DC converter 40 is in itself known and will here be referred to solely as regards the aspects necessary for understanding the problems lying at the basis of the present invention. In particular, it is pointed out that the DC-DC converter 40 presents two operating modes. A first operating mode is that in which the current error amplifier prevails over the voltage error amplifier and carries out regulation of the battery charging current, during which the charging current is constant at the programmed value and the voltage present across the battery increases from the initial value, typically zero, to its full charge value, whereas the second operating mode is that in which the voltage error amplifier prevails over the current error amplifier and carries out regulation of the voltage of the battery, during which the charging current decreases until it goes to zero and the battery voltage remains fixed at the full charge value.
Both of the DC-DC converters described above present a drawback due to the fact that the time of intervention of the CURL comparator 34 for limiting the current supplied by the DC-DC converters when overloads are present at output (for example, upon switching-on of the DC-DC converters when the capacitor 18 must be charged) is not zero and depends on the response time with which the DC-DC converters react to such variations.
Consequently, in the cases where heavy overloads or short circuits at output, or else at switching-on, occur, the CURL comparator 34 by itself does not suffice to limit the output current in that, in these conditions, the inductor 16 is charged with a current having a slope greater than the slope with which it is discharged, thus leading to a divergence of the output current.
In the literature there exist various methods for creating a current limitation system that is effective against short circuits and overloads.
A very well known method is based upon the so-called principle of frequency translation, i.e., based upon the reduction of the switching frequency of the DC-DC converter in the presence of overloads or short circuits, that is upon the reduction of the switching frequencies of the switches 6 and 8.
In FIG. 3 there is illustrated and designated by 60 a frequency translation DC-DC converter, usable as a voltage regulator.
The DC-DC converter 60 presents a circuit topology very similar to that of the DC-DC converter 1; for this reason, identical parts or parts equivalent to those of the DC-DC converter 1 will be identified with the same reference numbers.
The DC-DC converter 60 differs from the DC-DC converter 1 by further comprising a frequency translator 62 presenting a pair of input terminals 62a, 62b connected to the inverting and non-inverting terminals of the voltage error amplifier 28 and receiving, respectively, the division voltage VFB and the reference voltage VREF, and an output terminal 62u issuing a translation regulating signal supplied to an input terminal of the oscillator 32 and consisting of a bias current IBIAS for the oscillator 32 itself, which is designed so as to supply at an output a comparison voltage VC of a sawtooth or triangular waveform, the frequency whereof is proportional to the bias current IBIAS.
The operation of the DC-DC converter 60 is in itself known and will here be referred to solely as regards the aspects necessary for understanding the problems lying at the basis of the present invention. In particular, in conditions of short circuit or switching-on of the DC-DC converter 60, the output voltage VOUT is initially zero, in that the capacitor 18 is discharged, the bias current IBIAS supplied to the oscillator 32 assumes a minimum value, the comparison voltage VC supplied by the oscillator 32 consequently assumes a minimum value, and hence the switching frequency of the switches 6 and 8, which is controlled by the driving stage 10 and is in turn a function of the frequency of the comparison voltage VC, also assumes its minimum value.
As the output voltage VOUT increases, the bias current IBIAS increases accordingly, and the switching frequency of the switches 6, 8 tends to go to its nominal value.
A frequency translator 62 of the type described above is not, however, usable in the DC-DC converter 40 operating as a battery charger on account of the presence of the dual operating mode, i.e., as a current regulator and as a voltage regulator, of the DC-DC converter 40.
In fact, in both operating modes, under normal operating conditions, the DC-DC converter 40 should function at the nominal switching frequency; instead, with the frequency translation modality illustrated in FIG. 3 this is not possible in that, during the current regulation operating mode, since the output voltage VOUT varies from the zero value to the nominal value, the frequency translator 62 would control translation of the switching frequency of the DC-DC converter 40 even though no overload is present at output.